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  1.     OUTPUT "op_IY_BIT_FDCB_no_lua.bin"
  2.  
  3.     ;;; generate shift instructions: #FDCBFF00 .. #FDCBFF3F ("iy-1" = FF index byte)
  4.     DEFARRAY instructions rlc, rrc, rl, rr, sla, sra, sli, srl
  5.     DEFARRAY registers <(iy-1),b>, <(iy-1),c>, <(iy-1),d>, <(iy-1),e>, <(iy-1),h>, <(iy-1),l>, <(iy-1)>, <(iy-1),a>
  6.  
  7. INS_I=0
  8.     DUP 8
  9. REG_I=0
  10.         DUP 8
  11.             instructions[INS_I] registers[REG_I]
  12. REG_I=REG_I+1
  13.         EDUP
  14. INS_I=INS_I+1
  15.     EDUP
  16.  
  17.     ;;; generate `bit` instructions: #FDCBFF46 .. #FDCBFF7E (two: {#x6, #xE})
  18. REG_BIT=0
  19.     DUP 8
  20.         bit REG_BIT,(iy-1)
  21. REG_BIT=REG_BIT+1
  22.     EDUP
  23.  
  24.     ;;; generate `res` + `set` instructions: #FDCB1180 .. #FDCB11FF ("iy+17" = 11 index byte)
  25.     DEFARRAY instructions2 res, set
  26.     DEFARRAY registers2 <(iy+17),b>, <(iy+17),c>, <(iy+17),d>, <(iy+17),e>, <(iy+17),h>, <(iy+17),l>, <(iy+17)>, <(iy+17),a>
  27.  
  28. INS_I=0
  29.     DUP 2
  30. REG_BIT=0
  31.         DUP 8
  32. REG_I=0
  33.             DUP 8
  34.                 instructions2[INS_I] REG_BIT,registers2[REG_I]
  35. REG_I=REG_I+1
  36.             EDUP
  37. REG_BIT=REG_BIT+1
  38.         EDUP
  39. INS_I=INS_I+1
  40.     EDUP
  41.